Ts7300
This page contains my notes about the Technologic Systems TS-7300 SBC
Hand-building a toolchain
Contents |
General Resources
TS-7300 Manual
TS-7300 Schematic
My Specs
64MB RAM (TS-7300-64)
XBee & CF expansion card (TS-RF2-ZIGBEE / TS-RF2-CF) - schematic / XBee Getting Started / CF Getting Started
RTC (OP-BBRTC)
RoHS (OP-ROHS-NC)
Temperature Sensor (OP-TMPSENSE) - datasheet
2x24 Backlit LCD (LCD-LED)
Keypad (KPAD)
Enclosure with CAN bus (TS-ENC730 & OP-730CAN) - manual
General Info
Jumpers
The jumper pins on the mainboard allow basic configuration of a few things:
1 | Boot Serial |
2 | Console Enable |
3 | Write Enable Flash |
4 | Console is COM2 |
5 | TS_Test |
6 | Reserved (a TS kernel and initrd will treat this as 'fast boot') |
CPU
It's a Cirrus EP9302 ARM9 @ 200Mhz
It appears to have internal boot ROM that can boot from Flash, SPI, or UART... see #Boot EEPROM for more info
The Standard Boot Procedure
EEPROM
Physically it is the only 8-pin DIP on the board... near the CPU
See bottom left of the schematic - pg 4
The chip that is on my board appears to be a CSI 25160LI... but good luck getting a datasheet for it! (I found 1... in Chinese)
It seems to be compatible with the microchip 26LC160
Here is the Logic session if you want to check for yourself!
Here is the captured image... I plan to disassemble it and would advise against using it right now!
I managed to find the TS bootloader text streaming from the chip at power up
>> TS-SDBOOT - built Jan 26 2007 >> Copyright (c) 2007, Technologic Systems
See pg 119 of the EP9302 datasheet for more info on the Boot Procedure
It appears that the outer-side of JP1 is connected to 3v3, and the inner-side of JP1 is connected to BOOT0
The pre-burned image has a header of 'CRUS' (see EP9302 - pg 120 for more) - I guess this has something to do with endian-ness, as apparently 'SURC' is also accepted
The CPU will only read 2k from either UART, SPI or FLASH. That 2k must do everything else!
The 2k is read into the Ethernet buffer at address 0x80014000
The CPU will be in SVC mode (whatever that is...)
TS-SDBOOT
The data copied into the Ethernet buffer (from EEPROM) is know by Technologic Systems as TS-SDBOOT
It initializes SDRAM, bus timings, MAC addresses and performs self tests
TS-SDBOOT will now examine the 36 byte security block (last 36 bytes of EEPROM) and perform a few checks (see TS-7300 Manual - pg 14/15 for more)
After this is complete, TS-SDBOOT loads the first 512 bytes of the SD card to RAM at 0x1000, and then jumps execution to this memory address (in ARM Thumb mode...)
2 parameters are passed at this point:
- r0 contains the address of a routine that reads blocks from the SD card
void sdread(unsigned int start_sector, char *buffer, int num_sectors)
- r1 contains the address of a routine that outputs messages to the serial port (I assume the console port)
void ser_puts(char *buffer)
The first 440 bytes of sector 0 contain Thumb code that loads:
- The first partition with an ID/type of 0xDA (Non-FS data) as a kernel image into RAM location 0x218000
- The next partition with ID of 0xDA as an initrd to 0x1000000
Linux ATAGs are created, and its over to the kernel!
The Kernel
The Kernel is started with ATAGs describing the initrd and other things
XBee Socket
It appears to have an LM1117 (800mA voltage regulator) which is shared with the CF card, JTAG chip, CPLD, and data buffer... All I care is that it runs an XBee pro okay
The XBee pins that are connected are as follows:
XBee Pin | Signal | Signal | CPLD Pin |
---|---|---|---|
2 | DOUT | XBEE_RXD | 2 |
3 | DIN | XBEE_TXD | 3 |
5 | RESET# | XBEE_RESET# | 4 |
9 | DTR# | DTR# | 99? |
12 | DIO7 / CTS# | XBEE_CTS# | 1 |
16 | DIO6 / RTS# | RTS# | 97? |