Ts7300
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The CPU will only read 2k from either UART, SPI or FLASH. That 2k must do everything else!<br> | The CPU will only read 2k from either UART, SPI or FLASH. That 2k must do everything else!<br> | ||
{{note|This 2048 bytes does not include the trailing 'CRUS' that appears in the trace... but DOES include the preceding 'CRUS'}} | {{note|This 2048 bytes does not include the trailing 'CRUS' that appears in the trace... but DOES include the preceding 'CRUS'}} | ||
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+ | <h1>XBee Seat</h1> | ||
+ | It appears to have an [http://attie.co.uk/files/LM1117.pdf LM1117] (800mA voltage regulator) which is shared with the CF card, JTAG chip, CPLD, and data buffer... All I care is that it runs an XBee pro okay |
Revision as of 19:20, 8 June 2010
This page contains my notes about the Technologic Systems TS-7300 SBC
Contents |
General Resources
TS-7300 Manual
TS-7300 Schematic
My Specs
64MB RAM (TS-7300-64)
XBee & CF expansion card (TS-RF2-ZIGBEE / TS-RF2-CF) - schematic / XBee Getting Started / CF Getting Started
RTC (OP-BBRTC)
RoHS (OP-ROHS-NC)
Temperature Sensor (OP-TMPSENSE) - datasheet
2x24 Backlit LCD (LCD-LED)
Keypad (KPAD)
Enclosure with CAN bus (TS-ENC730 & OP-730CAN) - manual
General Info
Jumpers
The jumper pins on the mainboard allow basic configuration of a few things:
1 | Boot Serial |
2 | Console Enable |
3 | Write Enable Flash |
4 | Console is COM2 |
5 | TS_Test |
6 | Reserved |
CPU
It's a Cirrus EP9302 ARM9 @ 200Mhz
It appears to have internal boot ROM that can boot from Flash, SPI, or UART... see #Boot EEPROM for more info
Boot EEPROM
Physically it is the only 8-pin DIP on the board... near the CPU
See bottom left of the schematic - pg 4
The chip that is on my board appears to be a CSI 25160LI... but good luck getting a datasheet for it! (I found 1... in Chinese)
It seems to be compatible with the microchip 26LC160
Here is the Logic session if you want to check for yourself!
Here is the captured image... I plan to disassemble it and would advise against using it right now!
I managed to find the TS bootloader text streaming from the chip at power up
>> TS-SDBOOT - built Jan 26 2007 >> Copyright (c) 2007, Technologic Systems
See pg 119 of the EP9302 datasheet for more info on the Boot Procedure
It appears that the outer-side of JP1 is connected to 3v3, and the inner-side of JP1 is connected to BOOT0
The pre-burned image has a header of 'CRUS' (see EP9302 - pg 120 for more) - I guess this has something to do with endian-ness
The CPU will only read 2k from either UART, SPI or FLASH. That 2k must do everything else!
XBee Seat
It appears to have an LM1117 (800mA voltage regulator) which is shared with the CF card, JTAG chip, CPLD, and data buffer... All I care is that it runs an XBee pro okay