Makefile simple

This is a really simple makefile, for small projects

It will just build all of the *.c files in this directory into their own object files, and then output a linked binary to BINOUT

# the output binary name
BINOUT?=main
 
# a cross compile prefix (if you want one)
CROSS_COMPILE?=
 
# standard cflags
CFLAGS:=-Wall -pedantic
# standard lflags
LFLAGS:=
 
# a list of libraries you wish to link against
LIBS:=
 
#-------------------------------#
 
SRCS:=$(wildcard *.c)
DEPS:=$(addprefix .dep/,$(SRCS:.c=.d))
OBJS:=$(addprefix .obj/,$(SRCS:.c=.o))
 
LFLAGS+=$(addprefix -l,$(CLIBS))
 
GCC:=$(CROSS_COMPILE)gcc
MAKE+=--no-print-directory
 
.PHONY: all run clean new .%.dir
 
all: $(BINOUT)
 
run: all
	./$(BINOUT)
 
clean:
	rm -f $(DEPS) $(OBJS) $(BINOUT)
 
new: clean
	@$(MAKE) all
 
.%.dir:
	@if [ ! -d $* ]; then echo "mkdir -p $*"; mkdir -p $*; else echo "!mkdir $*"; fi
	@touch $@
 
$(BINOUT): $(OBJS)
	$(GCC) $(LFLAGS) $(filter %.o,$^) -o $@
 
$(OBJS): .obj/%.o: %.c ..obj.dir .dep/%.d
	$(GCC) $(CFLAGS) $*.c -c -o $@
 
$(DEPS): .dep/%.d: %.c ..dep.dir makefile
	$(GCC) $(CFLAGS) -MM -MT .obj/$*.o $*.c -o $@
 
include $(wildcard .dep/*.d)